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? mono and colour digital video cmos image sensors cd5404-6404f-a 1/54 vv5404 & VV6404 description vv5404 and VV6404 are highly integrated cmos vlsi sensors which enables high standards of performance and image quality at a very cost-effective price point. the 356 x 292 monochrome device offers one of the simplest routes currently available to design-in of imaging applications, while the colour device is ideal for low cost pc camera applications. both devices incorporate a comprehensive range of on-board controls eliminating the need for additional support chips. on- chip a/d conversion provides 8 bit digital output and the device set up is fully automatic via the built-in automatic black level calibration algorithm. exposure and gain settings are programmable and operation is controlled via a serial interface. this sensors offer variable frame rates of up to 30 frames per second and a 4 wire digital video bus. the digital interface also provides a tri-stateable data qualification clock and frame synchronisation signal. hand-held products, in applications such as pdas, bar code scanning or automatic meter reading, will benefit from the low power requirements and from the inbuilt sleep and power down modes. the price and performance standards introduced with the vv5404 and VV6404 enable use of an imaging solution where previously it may not have been practicable on cost grounds. block diagram features ? cif format mono or colour pixel array ? up to 30 frames per second operation ? on-chip 8 bit analogue to digital converter ? low power consumption ? up to 356 x 292 pixel image size ? automatic exposure and gain control ? serial interface control ? programmable exposure and gain values ? automatic black level calibration ? 4-wire digital video bus ? evaluation kit available applications ? pc cameras ? biometrics ? inspection systems specifications important: 1. a colour co-processor is required to convert the VV6404 sensors video data stream of raw colourised pixel data into either a cif or qcif for- mat rgb or yuv colour image. 2. vv5404 and VV6404 do not have any form of automatic exposure control. this must be performed externally. sample & hold horizontal shift photo diode analog voltage refs. sda scl d[3:0] vertical shift register clko 8-bit adc array register serial inter- face output format gain image format black calibration exposure registers stage oeb fst qck sin clki pixel resolution 356 x 292 (cif) array size 4.272mm x 3.212mm pixel size 12.0 m m x 11.0 m m min. illumination 0.1 lux exposure control automatic (to 25000:1) gain control automatic (to +20db) signal/noise ratio 46db supply voltage 5.0v dc +/- 5% supply current <75ma operating temperature (ambient) 0 o c - 40 o c (for extended temp. info please con- tact stmicroelectronics) package type 48lcc
vv5404 & VV6404 cd5404-6404f-a 2/54 table of contents 1. introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 image read-out options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 frame rate options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. exposure control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. digital video interface format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2 embedded control data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2.1 the combined escape and sync character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.2 the command word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.3 supplementary data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3 video timing reference and status/configuration data. . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.1 blank lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.2 black line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.3 valid video line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.4 start of frame line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.5 end of frame line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.4 detection of sensor using data bus state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.5 resetting the sensor via the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 power-up, low-power and sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.6.1 power-up/down (figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6.2 low-power mode (figure 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.6.3 sleep mode (figure 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.6.4 application of the system clock during sensor low-power modes . . . . . . . . . . . . . . . 22 4.7 qualification of output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7.1 using the external clock signal applied to cki . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7.2 data qualification clock, qck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.7.3 frame start signal, fst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. serial control bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 serial communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.3 data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.4 message interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.5 the programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.5.1 deviceh [000_00002] and devicel [000_ 00012] . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 status0 [000_00102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.5.3 line_count_h [000_00112] & line_count_l [000_01002]. . . . . . . . . . . . . . . . . . . . . 31 5.5.4 setup0 [001_00002] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.5.5 setup1 [001_00012] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.5.6 setup2 [001_00102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.5.7 setup4 [001_01002] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.5.8 setup5 [001_01012] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.5.9 exposure control registers [010_00002] - [010_10012]. . . . . . . . . . . . . . . . . . . . . . 35 5.5.10 adc setup register as0 [111_01112] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6 types of messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.1 single location, single data write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
vv5404 & VV6404 cd5404-6404f-a 3/54 5.6.2 single location, single data read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.6.3 no data write followed by same location read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.4 same location multiple data write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.6.5 same location multiple data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.6.6 multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.6.7 multiple location read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.7 serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6. clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.8 synchronising 2 or more cameras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 7. detailed specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7.2 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8. physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 8.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2 signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 48lcc mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 8.4 VV6404 sensor support circuit schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.5 sensor support circuit component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 9. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
vv5404 & VV6404 cd5404-6404f-a 4/54 1. introduction vv5404 and VV6404 are cif format cmos image sensors capable of outputing digital pixel data at frame rates, of upto 30 frames per second. the vv5404 is a monochrome part, while the VV6404 has a colour filter applied over the sensor array. important: the VV6404 sensors video data stream only contains raw colourised pixel data. a colour co-processor is required to generate for example either a cif or a qcif format yuv colour image. the 356 x 292 pixel sensors have an on-chip 8-bit analogue to digital converter (figure 1). the sensors offer very flexible digital interface, the main components of which are listed below: 1. a tri-stateable 4-wire data bus (d[3:0]) for sending both video data and em bedded timing references. 2. a data qualification clock, qck, which can be programmable via the serial interface to behave in a number of different ways (tri-stateable). 3. a frame start signal, fst (tri-stateable). 4. a 2-wire serial interface (sda,scl) for controlling and setting up the device. 5. the ability to synchronise the operation of multiple cameras - synchronisation input, sin. an 8-bit pixel value is transmitted across the 4 wire tri-stateable databus as series pair of 4-bit nibbles, most significant nibble first. along within the pixel data, codes representing the start and end frames and the start and end of lines are embedded within the video data stream to allow the video processor to s ynchronise with video data the camera module is generating. section 4. defines the format for the output video datastream. to complement the embedded control sequences a data qualification clock, qck, and a frame start si gnal are also available. qck can be set-up to either be: 1. disabled 2. free-running. 3. qualify only the control sequences and the pixel data. 4. qualify the pixel data only there is also the choice of two different qck f requencies, w here one is twice the f requency of the other. sample & hold horizontal shift photo diode analog voltage refs. sda scl d[3:0] vertical shift register clko 8-bit adc array register serial inter- face figure 1 : block diagram of vv5404 and VV6404 image sensors output format gain image format black calibration exposure registers stage oeb fst qck sin clki
vv5404 & VV6404 cd5404-6404f-a 5/54 1. fast qck: the falling edge of the clock qualifies the nibble data irrespective of whether it is the most or the least significant nibble. 2. slow qck: the rising edge of the clock qualifies the most significant nibbles while the f alling edge of the clock qualifies the least significant nibbles. the fst can be enabled/disabled via the serial interface. oeb tri-states all 4 databus lines, d[3:0], the qualification clock, qck and the frame start signal, fst. there are 3 main ways of interfacing to the vv5404 or VV6404 sensor based on the above signals: 1. the processor capturing the data (or colour co-processor for VV6404) supplies the sensor clock, cki, and uses the embedded control sequences to synchronise with the frame and line level timings. thus the processor and sensor are running off derivatives of the same fundamental clock (4 fsc - 14.31818 mhz). to allow the receiver to determine the best sampling position of the video data, during its power-up sequence the sensor outputs a 101010... sequence on each of its databus lines for the vi deo pr ocessor to lock on to. 2. the video processor uses a free-running qck supplied by the sensor to sample the incoming vi deo data stream. the embedded control sequences are used to synchronise the frame and line level timings. a crystal is used to generate the clock for the sensor. 3. the video processor uses fst and the data only mode for qck to synchronise to the incoming video data. pri- marily intended for interfacing to frame grabbers. the 2-wire serial interface provides complete control over how the sensor is setup and run. exposure and gain values are programmed via this interface. section 5. defines the communications protocol and the register map of all the locations which can be accessed via the serial interface. using the first two interface options outlined above it is possible to control the sensor and receive video data via a 9- wire cable between the sensor and the v ideo pr ocessor/colour-pr ocessor. 1. a 4-wire data bus (d[3:0]) for sending both video data and embedded timing references. 2. a 2-wire serial interface (sda,scl). 3. the clock for the sensor or qck from the sensor. 4. vcc and gnd power lines. the various image read-out and frame rate options are detailed in sections 2 and 3 respectively. figure 2 : interfacing options sda scl d[3:0] clki sensor colour co-processor (processor) sda scl d[3:0] qck sensor colour co-processor (processor) fst
vv5404 & VV6404 cd5404-6404f-a 6/54 2. operating modes 2.1 image read-out options the output image format is cif (352 x 288 pixel array). to provide the colour co-processor with the extra information it needs for interpolation at the edges of the VV6404 pixel array, an optional border 2 pixels deep on all 4 sides of the array can be enabled (figure 4). the resulting image size of 356 x 292 pixels is the default power up state for this camera module. the border option is programmable via the serial interface. image read-out is either non-interlaced raster scan, or shuffled non-interlaced raster scan. the shuffled raster scan order differs from a conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, followed by the even pixels. this shuffled read-out within a line, is useful in the VV6404 device as it groups pixels of the same colour (according to the bayer pattern - figure 3) together, reducing cross talk between the colour channels. note: this option is on by default in both vv5404 and VV6404 sensors and is controllable via the se rial interface. 2.2 frame rate options two options: 30 fps or 25 fps (assuming a 7.15909 mhz input clock and the default clock divider setting). the number of video lines in for each frame rate is the same (304), the slower frame rate is implemented by extending the line period from 393 pixel periods to 471 pixel periods. 30 fps is the default option, the frame rate is programmable via the serial interface. border image size (column x row) disabled 352 x 288 enabled 356 x 292 default table 1 : image format selection. frame rate (fps) frame timing (pixels x lines) 25 471 x 304 30 393 x 304 default table 2 : frame rate selection blue green green red even columns (0, 2, 4,...) odd columns (1, 3, 5,...) even rows (0, 2, 4,...) odd rows (1, 3, 5,...) figure 3 : bayer colourisation pattern. (VV6404 only)
vv5404 & VV6404 cd5404-6404f-a 7/54 blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red blue green green red 355 354 353 352 289 291 290 288 1 3 2 0 3 2 1 0 figure 4 : VV6404 colourised image format 352 pixels 288 pixels 292 pixels 356 pixels 0, 1, 2, 3,... ... 352, 353, 354, 355 0, 1, 2, 3,... ... 288, 289, 290, 291 border rows and columns pixel array
vv5404 & VV6404 cd5404-6404f-a 8/54 3. exposure control the exposure time for a pixel and the gain of the input amplifier to the 8-bit adc are programm able via the serial interface. the explanation below assumes that the gain and exposure values are updated together as part of a 5 byte serial interface auto-increment sequence. the exposure is divided into 2 components - coarse and fine. the coarse exposure value sets the number of lines a pixel exposes for, while the fine exposure sets the number of additional pixel clock cycles a pixel integrates for. the sum of the two gives the overall exposure time for the pixel array. 30 fps mode: exposure time = (clock divisor) x (coarse x 393 + fine) x (cki clock period)/ 25 fps mode: exposure time = (clock divisor) x (coarse x 471 + fine) x (cki clock period) if an exposure value is loaded outwith the valid ranges listed in the above table the value is clipped to lie within the above ranges. exposure and gain values are re-timed within the sensor to ensure that a new set of values is only applied to the sensor array at the start of each frame. bit 0 of the status register is set high when a new exposure value is written via the serial interface but has not yet been applied to the sensor array. there is a 1 frame latency between a new exposure value being applied to the sensor array and the results of the new exposure value being read-out. the same latency does not exist for the gain value. to ensure that the new exposure and gain values are aligned up correctly the sensor delays the application of the new gain value by one frame relative to the application of the new exposure value. to eliminate the possibility of the s ensor array seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the exposure page of the serial inter face register map. thus if the 5 by tes of exposure and gain data is sent as an auto-increment sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. value units 30 fps mode 25 fps mode min. max. min. max. coarse video lines 0 302 0 302 fine pixel clocks 0 356 0 434 table 3 : coarse and fine exposure ranges. gain code, g[2:0] amplifier gain 000 1 001 2 011 4 111 8 table 4 : main gain steps.
vv5404 & VV6404 cd5404-6404f-a 9/54 4. digital video interface format 4.1 general description the video interface consists of a unidirectional, tri-stateable 4-wire databus. the nibble transmission is synchronised to the rising edge of the system clock (figure 13). digital video data is 8 bits per sample, transmitted as serial pairs of parallel 4-bit nibbles (most significant nibble first) on 4 wires. multiplexed with the sampled pixel data is control information including both video timing references and sensor status/configuration data. video timing reference information takes the form of field start characters, line start characters, end of line characters and a line counter. where hexadecimal values are used, they are indicated by a subscript h, such as ff h ; other values are decimal. 4.2 embedded control data to distinguish the control data from the sampled video data all control data is encapsulated in embedded control sequences. these are a minimum of 6 words long and includes a combined escape/sync character, 1 control word (the command byte) and 2 words of supplementary data. to minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have been used to allow single bit errors in the embedded control words to be corrected. however, more serious corruption of control words or the corruption of escape/sync characters cannot be tolerated without loss of sync to the data stream. to ensure that a loss of sync is detected a simple set of rules has been devised. the four exceptions to the rules are outlined below: 1. data containing a command words that has two bit errors. 2. data containing two end of line codes that are not separated by a start of line code. 3. data preceding an end of frame code before a start of frame code has been received. 4. data containing line that do not have sequential line numbers (excluding the end of frame line). if the video processor detects one of th ese violations then it s hould abandon the current frame of video. 4.2.1 the combined escape and sync character each embedded control sequence begins with a combined escape and sync character that is made up of three words. the first two of these are ff h ff h - constituting two words that are illegal in normal data. the next word is 00 h - guaranteeing a clear signal transition that allows a video processor to determine the position of the word boundaries in the serial stream of nibbles. combined escape and sync c haracters are always followed by a command word - making up the four word minimum embedded control sequence. 4.2.2 the command word the word that follows the combined escape/sync characters defines the type of embedded control data. three of the 8 bits are used to carry the control information, four are parity bits that allow the video processor to detect and correct a certain level of errors in the transmission of the command words, the remaining bit is always set to 1 to ensure that the command word is never has the value 00 h . the coding scheme used allows the correction of single bit errors (in the 8-bit sequence) and the detection of 2 bit errors. the th ree data bits of the command word are interpreted as shown in figure 5. read-out order progressive scan (non-interlaced) form of encoding uniformly quantised, pcm, 8 bits per sample correspondence between video signal levels and quantisation levels: internally valid pixel data is clipped to ensure that 00 h and ff h values do not occur when pixel data is being output on the data bus. this gives 254 possible values for each pixel (1 - 254). the video black level corresponds to code 16. table 5 : video encoding parameters
vv5404 & VV6404 cd5404-6404f-a 10/54 figure 5 : embedded control sequence (i) line number (l 11 msb) (line code) escape/sync sequence bit 76543210 odd word parity f h f h f h f h 0 h 0 h y h x h d 2 d 3 d 0 d 1 p 2 p 3 p 1 p 0 or (ii) if line code = end of line then nibble x h nibble y h nibble d 3 nibble d 2 nibble d 1 nibble d 0 nibble d 3 = f h nibble d 1 = f h nibble d 2 = f h nibble d 0 = f h line code nibble x h nibble y h 1 c 2 c 1 c 0 p 3 p 2 p 1 p 0 end of line 1000 2 (8 h )0000 2 (0 h ) blank line (bl) 1001 2 (9 h ) 1101 2 (d h ) black line (bk) 1010 2 (a h ) 1011 2 (b h ) visible line (vl) 1011 2 (b h )0110 2 (6 h ) start of frame (sof) 1100 2 (c h )0111 2 (7 h ) end of frame (eof) 1101 2 (d h ) 1010 2 (a h ) reserved 1110 2 (e h ) 1100 2 (c h ) reserved 1111 2 (f h )0001 2 (1 h ) bit 76543210 c 2 1 c 1 c 0 l 7 l 8 l 6 p l 11 0 l 10 l 9 l 1 l 2 l 0 p l 5 0 l 4 l 3 1 1 11 1 1 11 1 1 11 1 1 11 supplementary data command 4-wire nibble output mode
vv5404 & VV6404 cd5404-6404f-a 11/54 sof line 2 black lines (bk) 7 blank lines (bl) 292 visible lines (vl) start of image (sof) bk bk bl bl bl vl vl vl vl vl vl vl vl sof bk eof bl 303 123 4 9101112 13 299 298 300 301 1 303 number line code figure 6 : frame formats start of blanking end of image data frame frame start of frame frame period (304 lines) bl lines black lines 0 0 302 blanking line end of image (eof) start of blanking end of image data frame frame start of frame lines black lines blanking lines sof 2 black lines (bk) 9 blank lines (bl) 288 visible lines (vl) start of image (sof) bk bk bl bl bl vl vl vl vl sof bk eof bl 303 123 4 9101112 13 299 298 300 301 1 303 frame period (304 lines) bl 0 0 302 end of image (eof) bl bl bl bl frame format (border rows and columns enabled - default) : frame format (border rows and columns disabled)) : line number line code
vv5404 & VV6404 cd5404-6404f-a 12/54 start of active video (sav) line figure 7 : line data format. end of active video (eav) video data 178 odd pixels 178 even pixels 0 h y h d 1 d 0 d 3 d 2 p m p l p m p l p m p l p m p l f h line format p m p l p m p l number sav line period (393 pixel periods - 30 fps, 471 pixel periods - 25 fps) 1 3 355 0 352 354 356 pixels pixel number (shuffled pixel data) f h f h f h f h f h f h 0 h 0 h 8 h 0 h 0 h x h line code escape/sync sequence null characters line code escape/sync sequence 4-wire nibble output mode, d[3:0] 0 1 177 178 354 355 pixel number (unshuffled pixel data) p m = pixel value - most significant nibble, p l = pixel value - least significant nibble, p = 8-bit pixel value (i) (ii) (iii) (iv) (v) blanking line (bl) black line (bk) visible line (vl) start of frame (sof) end of frame (eof) p = blanking level (07 h ) p = valid black pixel data p = valid pixel data p = sensor status data p = blanking level (07 h )
vv5404 & VV6404 cd5404-6404f-a 13/54 the even parity bits are based on the following relationships: 1. an even number of ones in the 4-bit sequence (c 2 , c 1 , c 0 and p 0 ). 2. an even number of ones in the 3-bit sequence (c 2 , c 1 , p 1 ). 3. an even number of ones in the 3-bit sequence (c 2 , c 0 , p 2 ). 4. an even number of ones in the 3-bit sequence (c 1 , c 0 , p 3 ). table 6 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors. 4.2.3 supplementary data the last 2 bytes of the embedded control sequence contains supplementary data. this normally contains the current line number except if the line code is the end of line, the 2 bytes are padded out using null characters (ff h ). the 12 bit line number is packaged up by splitting it into two 6-bit values. each 6-bit values is then converted into an 8-bit value by adding a zero to the start and an odd word parity bit at the end. 4.3 video timing reference and status/configuration data the video sequence is made up of lines of data. each field of data is constructed of the fo llowing data lines: 1. a start of frame line 2. 2 of black lines (used for black level calibration) 3. 7 (9) of blank lines 4. 292 (288) active video lines 5. an end of frame line 6. 1 (3) blank lines the numbers given in () are for when the border rows and columns are not output on the databus. each line of data starts with an embedded control s equence that ide ntifies the line type (as outlined in table 3). the control sequence is then followed by two bytes that, except in the case of the end-of-frame line, contain a coded line number. the line number sequences starts with the start-of-frame line at 00 h and increments one per line up until the end-of-frame line. each line is terminated with an end-of-line embedded control sequence. the line start embedded sequences must be used to recognise data lines as a number of null bytes may be inser ted between data lines. parity checks comment p 3 p 2 p 1 p 0 1 1 1 1 code word un-corrupted 1110p 0 corrupted, line code ok 1101p 1 corrupted, line code ok 1011p 2 corrupted, line code ok 0111p 3 corrupted, line code ok 0010c 0 corrupted, invert sense of c 0 0100c 1 corrupted, invert sense of c 1 1000c 2 corrupted, invert sense of c 2 all other codes 2-bit error in code word. table 6 : detection of 1-bit and 2-bit errors in the command word
vv5404 & VV6404 cd5404-6404f-a 14/54 4.3.1 blank lines in addition to padding between data lines, actual blank data lines may appear in the positions indicated above. these lines begin with start-of-blank-line embedded control sequences and are construc ted identically to active vi deo lines except that they will contain only blank bytes (07 h ). 4.3.2 black line timing the black lines (which are used for black level calibrati on) are identical in structure to valid v ideo lines except that they begin with a start-of-black line sequence and contain either information from the sensor black lines or blank bytes (07 h ). 4.3.3 valid video line timing all valid video data is contai ned on active video lines. the pixel data appears as a continuous stream of bytes within the active lines. the pixel data may be separated from the line header and end-of-line control sequence by a number of blank bytes (07 h ), e.g. when the border lines and pixels are disabled 07 h is output in place of pixels 0, 1, 354 and 355. 4.3.4 start of frame line timing the start of frame line which begins each video field contains no vi deo data but inst ead contains the contents of all the serial interface registers. this information follows the start-of-line header immediately and is terminated by an end-of-line control sequence. to ensure that no escape/sync characters appear in the sensor status/configuration information the code 07 h is output after each serial interface value. thus it takes 256 pixel clock periods (512 system clocks) to output all 128 of the serial inter face registers. the remainder of the 356 pi xel periods of the vi deo portion of the line is padded out using 07 h values. the first two pixel locations are also padded with 07 h characters (figure 8) if a serial interface register location is unused then 07 h is output. the read-out order of the registers is independent of whether the pixel read-out order is shuffled or un-shuffled. 4.3.5 end of frame line timing the end of frame line which begins each video field contains no video data. its sole purpose is to indicate the end of a frame. 4.4 detection of sensor using data bus state the video processor device must have inter nal pull-down terminations on the data bus. on power-up a sensor will pull all data lines high for a guaranteed period. this scheme allows the pres ence of a sensor on the interface to be detected by the video processor on power-up, and the connection of a sensor to an already power-up interface (a hot connection). the absence of a sensor is detected by the video processor seeing more than 32 c onsecutive nibbles of 0 h on the data bus. on detecting the absence of a s ensor, cki, s hould be disabled (held low). the presence of a sensor is detected by the video processor seeing more than 32 consecutive nibbles of f h on the data bus. on detecting the pres ence of a sensor, cki, should be enabled. 4.5 resetting the sensor via the serial interface bit 2 of setup register 0 allows the VV6404 sensor to be reset to its power-on state via the 2-wire serial interface. setting this soft reset bit causes all of the serial interface registers including the soft reset bit to be reset to their default values. this soft reset leaves the sensor in low-power mode and thus an exit low-power mode command (section 4.6.2) must be issued via the serial interface before the sensor will start to generate video data (figure 9). 4.6 power-up, low-power and sleep modes to clarify the state of the interface on power-up and in the case of a hot connection of the interface cable the power- up state of the bus is defined below.
vv5404 & VV6404 cd5404-6404f-a 15/54 start of active video figure 8 : status line data format. end of active video serial interface register values 0 h 1 h 0 h 1 h 0 h 7 h f h f h f h output databus, d[3:0] 1 h 9 h (sav) (eav) c h 7 h 0 h 7 h 0 h 7 h 4 h 0 h 0 h 7 h 0 h 7 h 0 h 7 h 8 h 0 h 0 h 0 h start of frame line code line number 0 deviceh (register 0) devicel (register 1) padding characters
vv5404 & VV6404 cd5404-6404f-a 16/54 figure 9 : resetting the VV6404 sensor via the serial interface. f h 9 h ,6 h ,9 h ,6 h ... n 0 1 d[3:0] clki frame number sda scl 2 3 4 5 start of frame line for the 1st frame of valid video data. valid video data. sr0 sr1 sr2 sr6 sr7 setup0[2] sr0-sr1 soft-reset command. at the end of the command the sensor is reset and enters low-power mode. sr2 the sensor enters low-power mode. sr3-sr4 exit low power mode command. powers-up analogue circuits and initiates the vm6404 sensors 4-frame start-up sequence sr5-sr6 1 frame of alternating 9 h & 6 h data on d[3:0] for the video processor to determine the best sampling phase for the nibble data (d[3:0]). sr7-sr8 4 frames after the exit low-power mode command, the sensor starts outputing valid video data. one frame of 9 h & 6 h data. f h sr3 sr4 sr5 sr8 setup0[0]
vv5404 & VV6404 cd5404-6404f-a 17/54 pu0 system power up or sensor hot plugged pu1 sensor internal-on reset triggers, the sensor enters low power mode and d[3:0] is set to f h . pu2 video processor released from reset. pu3 video processor enables the sensor clock, clki. pu4-pu5 at least 16 clki clock periods after clki has been enabled the vp sends a soft-reset command to the sensor via the serial interface. this ensures that if a sensor is present then it is in low-power mode. pu6 on detecting 32 consecutive f h values on d[3:0], the video processor sets the no_camera low. pu7-pu8 if present, upload the sensor defect map from e 2 prom into the video processor pu9 video processor disables the sensor clock, clki. pu10 video processor generates the vp_ready interrupt. pu11 the host software services the vp_ready interrupt. pu12 host issues command to remove sensor from low-power mode. vp enables the sensor clock, clki. pu13-pu4 at least 16 clki clock periods after clki has been enabled the vp sends the exit low- power mode command to the sensor via the serial interface. this initiates the sensors 4 frame start sequence. pu15-pu16 one frame of alternating 9 h & 6 h data on d[3:0] for the video processor to determine the best sampling phase for the nibble data (d[3:0]). pu17-pu18 4 frames after the exit low-power mode serial comms, the sensor starts outputing valid video data. table 7 : system power-up or hot-plugging device behaviour
vv5404 & VV6404 cd5404-6404f-a 18/54 4.6.1 power-up/down (figure 12) on power-up all of the databus lines will go high immediately (f h ), to indicate that the device is present and the device enters it low-power mode (section 4.6.2). when the video processor is reset the following sequence should be executed to ensure that the vm6404 starts to generate video data: 1. after the video processor has been released from reset, the sensor clock, clki, should be enabled immedi- ately 2. after waiting for at least 16 clki clock cycles, a soft reset command should be issued to the sensor. this is necessary to ensure that the sensor is brought into a known state. if the sensor is not present then the serial interface communications by video processor will not be acknowledged. 3. poll for 32 consecutive f h values on the data bus, if this condition is satisfied then the sensor is present. the video processor should set the camera_present flag. 4. determine if the serial cmos e 2 prom containing the defectivity map for the sensor is present and down-load the values. 5. disable the sensor clock cki. 6. the video processor should generate the vp_ready interrupt. 7. once the host software serviced the vp_ready interrupt, then the sensor and video processor is ready to gen- erate video data. 8. to enable video data, the host software, sets the low-power mode bit low. the video processor must enable clki at least 16 clki clock cycles before issuing the exit low-power mode command via the serial interface. after the exit low-power mode command has been sent the sensor will output for one frame, a continuous stream of alternating 9 h and 6 h values on d[3:0]. by locking onto the resulting 0101/1010 patterns appearing on the data bus lines the video processor can determine the best sampling position for the nibble data. after the last 9 h 6 h pair has been output the databus returns to f h until the start of fifth frame after cki has been enabled when the first active frame output. after the video processor has determined the correct sampling position for the data, it should then wait for the next start of frame line (sof). if the video processor detects 32 consecutive 0 h values on the data bus, then the sensor has been removed. the sensor clock, cki, should be held low. 4.6.2 low-power mode (figure 10) under the control of the serial interface the sensor analogue circuitry can be powered down and then be powered up. when the low-power bit is set via the serial interface, all the databus lines will go high at the end of the end of frame line of the current frame. at this point the analogue circuits in the sensor will power down. the system clock must remain active for the duration of low power mode. only the analogue circuits are powered down, the values of the serial interface registers e.g. exposure and gain are preserved. the internal frame timing is reset to the start of a video frame on exiting low-power mode. in a similar manner to the previous section, the first frame after the serial comms contains a continuous stream of alternating 9 h and 6 h to allow the video processor to re-confirm its sa mpling positi on. then three frames latter the first start of frame line is generated. 4.6.3 sleep mode (figure 11) sleep mode is similar to the low-power mode, except that anal ogue circuitry remains powered. when the sl eep command is received via the serial interface the pixel array will be put into reset and the data lines all will go high at the end of the current frame. again the system clock must remain active for the duration of sleep mode. when sleep mode is disabled, the cmos sensors frame timing is reset to the start of a frame. during the first frame after exiting from sleep mode the databus will remain high, while the exposure value prop agates thr ough the pixel array. at the start of the second frame the first start of field line will be generated.
vv5404 & VV6404 cd5404-6404f-a 19/54 figure 10 : entering and exiting low power mode. n 0 1 d[3:0] clki frame number sda scl 2 3 4 5 start of frame line for the 1st frame of valid video data. valid video data. lp0 lp1 lp3 lp2 lp7 lp8 setup0[0] lp0-lp1 enter low power mode command. lp2 at end of current frame, d[3:0] is set to f h and the vm6404 sensors analogue circuitry is powered down. lp3-lp4 exit low power mode command. powers-up analogue circuits and initiates the vm6404 sensors 4-frame start-up sequence lp5-lp6 1 frame of alternating 9 h & 6 h data on d[3:0] for the video processor to determine the best sampling phase for the nibble data (d[3:0]). lp7-lp8 4 frames after the exit low power mode command, the sensor starts outputing valid video data. one frame of 9 h & 6 h data. f h f h 9 h ,6 h ,9 h ,6 h ... lp4 lp5 lp6
vv5404 & VV6404 cd5404-6404f-a 20/54 figure 11 : entering and exiting sleep mode. n 0 1 d[3:0] clki frame number sda scl 2 3 4 5 start of frame line for the 1st frame of valid video data. valid video data. sl0 sl1 sl3 sl2 sl7 setup0[1] sl0-sl1 enter sleep mode command. sl2 at end of current frame, d[3:0] is set to f h . sl3-sl4 exit sleep mode command. powers-up analogue circuits and initiates the vm6404 sensors 1-frame sleep start-up sequence sl6-sl7 1 frame after the exit sleep mode command, the sensor starts outputing valid video data. f h sl4 sl5 sl6
vv5404 & VV6404 cd5404-6404f-a 21/54 figure 12 : system power-up or hot-plugging device behaviour 4 3 2 1 0 f h f h 5v 0v 2.8v 9 h ,6 h ,9 h ,6 h ... regulated sensor power d[3:0] clki frame number sda scl pu0 pu1 pu10 pu3 pu2 pu4 pu5 pu6 pu7 pu8 pu9 pu11 vp dev_reset pu12 start of frame line for the 1st frame of valid video data. vp_ready camera_present colour video processor one frame of 9 h & 6 h data. pu13 pu14 pu15 pu16 pu17 pu18 setup0[2] setup0[0]
vv5404 & VV6404 cd5404-6404f-a 22/54 4.6.4 application of the system clock during sensor low-power modes for successfully entry and exit into and out of low power and sleep modes the system clock, clki, must remain active for the duration of these modes. 4.7 qualification of output data there are two distinct ways for qualifying the data nibbles appearing of the output data bus 4.7.1 using the external clock signal applied to cki the data on the output data bus, changes on the rising edge of cki. the delay between the video processor supplying a rising clock edge and the data on the databus becoming valid, d epends on the length of the cable between the sensor and the video processor. to allow the video pr ocessor to find the best sampling position for the data nibbles, via the serial interface the databus can be forced to output continuously 9 h , 6 h , 9 h , 6 h ,... 4.7.2 data qualification clock, qck VV6404 provides a data qualification clock for the output bus. there are two frequencies for the qua lification clock: one runs at the nibble rate and the other at the pixel read-out r ate. the falling edge of the fast qck qualifies every nibble irrespective of whether it is most or least significant nibble. for the slow qck, the rising edge qualifies the most significant nibbles in the output data stream and the falling edge qualifies the least significant nibbles in the output data stream. there are 4 modes of operation of qck. 1. disabled (always low - (default) 2. free running - qualifies the whole of the output data stream. 3. embedded control sequences, status data and pixel data. 4. pixel data only. the operating mode for qck is set via the serial interface. the qck output is tristated when oeb is high.in one of the modes available via the serial interface the slow version of qck will appear on the qck pin while the fast version of the same signal will appear on the fst pin. in the case where the border rows and columns are disabled, there is simply no qualification pulse at that point in time i.e. when pixels 0,1, 354 and 355 are normally output. the qck pin can also be configured to output the state of a serial interface register bit. this feature allows the sensor to control external devices, e.g. stepper motors, shutter mechanisms. the configuration details for qck can be found in sections 5.5.7 and 5.5.8 of this document. 4.7.3 frame start signal, fst there are 3 modes of operation for the fst pin programmable via the serial interface: 1. disabled (always low- default). 2. frame start signal. the fst signal occurs once frame, is high for 356 pixel periods (712 system clock periods) and qualifies the data in the start of frame line. the fst is tristated when oeb is high. the fst pin can also be configured to output the state of a serial interface register bit. this feature allows the sensor to control external devices, e.g. stepper motors, shutter mechanisms. the configuration details for fst can be found in sections 5.5.7 and 5.5.8 of this document.
vv5404 & VV6404 cd5404-6404f-a 23/54 end of active video (eav) start of active video (sav) pixel data figure 13 : qualification of output data (border rows and columns enabled). video data f h line format 4-wire nibble output mode - d[3:0] d 1 d 0 f h f h f h p m p l p m p l p m p l p m p l crystal clock or external clock applied to cki slow qualification clock, qck (i) free running (ii) control sequences and pixel data (iii) pixel data only p m = pixel value - most significant nibble, p l = pixel value - least significant nibble, p = 8-bit pixel value fast qualification clock, qck (i) free running (ii) control sequences and pixel data (iii) pixel data only
vv5404 & VV6404 cd5404-6404f-a 24/54 sof line 2 black lines (bk) 7 blank lines (bl) 292 visible lines (vl) start of image (sof) bk bk bl bl bl vl vl vl vl vl vl vl vl sof bk eof bl 303 123 4 9101112 13 299 298 300 301 1 303 number line code figure 14 : frame level timings for fst and qck (border rows and columns enabled). start of blanking end of image data frame frame start of frame frame period (304 lines) bl lines black lines 0 0 302 blanking line end of image (eof) fst qck frame format (border rows and columns enabled - default) : (i) free running (ii) control plus data (iii) data only
vv5404 & VV6404 cd5404-6404f-a 25/54 figure 15 : frame level timings for fst and qck (border rows and columns disabled). fst qck (i) free running (ii) control plus data (iii) data only start of blanking end of image data frame frame start of frame lines black lines blanking lines sof 2 black lines (bk) 9 blank lines (bl) 288 visible lines (vl) start of image (sof) bk bk bl bl bl vl vl vl vl sof bk eof bl 303 123 4 9101112 13 299 298 300 301 1 303 frame period (304 lines) bl 0 0 302 end of image (eof) bl bl bl bl frame format (border rows and columns disabled) : line number line code
vv5404 & VV6404 cd5404-6404f-a 26/54 line number 303 1 2 3 9 10 11 300 start of blanking image data frame frame period (304 lines) lines black lines 0 fst frame format (border rows and columns enabled in example): end of frame 302 blanking line 301 1 303 end of frame start of frame 0 302 blanking line 2 black lines sav fst eav eav status information (i) frame start pulse - qualifies status line information. start of frame line format: line period (393 pixel periods - 30 fps, 471 pixel periods - 25 fps) 356 pixels 37 (115) pixels 4 pixels 33 (111) pixels figure 16 : fst pin waveforms.
vv5404 & VV6404 cd5404-6404f-a 27/54 5. serial control bus 5.1 general description writing configuration information to the video sensor and reading both sensor status and configuration information back from the sensor is performed via the 2-wire serial interface. communication using the serial bus centres around a number of registers internal to the video sensor. these registers store sensor status, set-up, exposure and system information. most of the registers are read/write allowing the receiving equipment to change their contents. others (such as the chip id) are read only. the main features of the serial interface include: ? variable length read/write messages. ? indexed addressing of information source or destination within the sensor. ? automatic update of the index after a read of write message. ? message abort with negative acknowledge from the master. ? byte oriented messages. the contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line - see section 4.3.4. 5.2 serial communication protocol the video processor must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.the communication from host to camera takes the form of 8-bit data with a maximum serial clock video processor frequency of up to 100 khz. since the serial clock is generated by the host it determines the data transfer rate. the bus address for the sensor in VV6404 is 20 h and for the serial e 2 prom containing the defect map it is a0 h . data transfer protocol on the bus is shown below. 5.3 data format information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. the internal data is produced by sampling sda at a rising edge of scl . the external data must be stable during the high period of scl . the exceptions to this are start (s) or stop (p) conditions when sda falls or rises respectively, while scl is high. a message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (sr), followed by another message. the first byte contains the device address byte which includes the data direction read, (r) , ~write , (~w), bit. the device address of VV6404 is fixed as 0010_000_[lsb] 2 . the lsb of the address byte indicates the direction of the message. if the lsb is set high then the master will read data from the slave and if the lsb is reset low then the master will write data to the slave. after the r,~w bit is sampled, the data direction cannot be changed, until the next address byte with a new r,~w bit is received. the byte following the address byte contains the address of the first data byte (also referred to as the index ). the serial interface can address up to 128, byte registers. if the msb of the second byte is set the automatic increment feature of the address index is selected. 12 7 8 a start condition stop condition sda scl acknowledge p s 3 4 56 address or data byte msb lsb figure 17 : serial interface data transfer protocol
vv5404 & VV6404 cd5404-6404f-a 28/54 5.4 message interpretation all serial interface communications with the sensor must begin with a start condition. if the start condition is followed by a valid address byte then further communications can take place. the sensor will acknowledge the receipt of a valid address by driving the sda wire low. the state of the read/~write bit (lsb of the address byte) is stored and the next byte of data, sampled from sda, can be interpreted. during a write sequence the second byte received is an address index and is used to point to one of the in ternal registers. the msbit of the following byte is the index auto increment flag. if this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. the master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start , (sr) . if the auto increment feature is used the master does not have to send indexes to accompany the data bytes. as data is received by the slave it is written bit by bit to a serial/parallel register. after each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addr essed by the current index. during a read message, the current index is read out in the byte following the device address byte. the next byte read from the slave device are the contents of the register addressed by the current index. the contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. at the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. although vv5404 and VV6404 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. at the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last location read from or written to. a subsequent read will use this index to begin retrieving data from the internal registers. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. s address[7:1] r / w bit a data[7:0] a sensor acknowledges valid address acknowledge from slave index[6:0] inc p a a data[7:0] [0] 0 0 1 0 0 0 0 address auto increment index bit figure 18 : serial interface data format
vv5404 & VV6404 cd5404-6404f-a 29/54 5.5 the programmers model there may be up to 128, 8-bit registers within the camera, accessible by the user via the se rial inter face. they are grouped according to function with each group occupying a 16-byte page of the location address space. there may be up to eight such groups, although this scheme is purely a conceptual feature and not related to the actual hardware implementation, the primary categories are given below: ? status registers (read only). ? setup registers with bit significant functions. ? exposure parameters that influence output image brightness. ? system functions and analogue test bit significant registers. any internal register that can be written to can also be read from. there are a number of read only registers that contain device status information, (e.g. design revision details). names that end with h or l denote the most or least significant part of the internal register. note that unused locations in the h byte are packed with zeroes. stmicroelectronics sensors that include a 2-wire serial interface are designed with a common address space. if a register parameter is unused in a design, but has been allocated an address in the generic design model, the location is referred to as reserved . if the user attempts to read from any of these reserved locations a default byte will be read back. in VV6404 this data is the lsbyte of the device status word, address 000_0000. a write instruct ion to a reserved (but unused) location is illegal and would not be successful as the device would not allocate an in ternal register to the data word contained in the instruction.
vv5404 & VV6404 cd5404-6404f-a 30/54 a detailed description of each register follows. the address indexes are shown as binary numbers in brackets []. index name length r/w default comments status 000_0000 deviceh 8 ro 0001 1001 2 chip identification number including revision indicator 000_0001 devicel 8 ro 0100 0000 2 000_0010 status0 8 ro 0000 1000 2 000_0011 line_counth 8 ro current line counter msb value 000_0100 line_countl 8 ro current line counter lsb value 000_0101 unused 000_011x unused 000_1xxx unused setup 001_0000 setup0 8 r/w 0001 0001 2 001_0001 setup1 8 r/w 1100 0001 2 001_0010 setup2 8 r/w 31 contains pixel counter reset value used by external sync. 001_0011 reserved 001_0100 setup4 8 r/w 0 fst and qck mode selects 001_0101 setup5 8 r/w 0 fst and qck mapping mode. 001_011x unused 001_1xxx unused exposure 010_0000 fineh 8 r/w 0 fine exposure. 010_0001 finel 8 r/w 010_0010 coarseh 8 r/w 302 coarse exposure 010_0011 coarsel 8 r/w 010_0100 gain 3 r/w 0 adc pre-amp gain setting 010_0101 clk_div 2 r/w 0 clock division 010_0110 unused 010_0111 unused 010_1xxx unused system 111_0000 reserved 111_0001 reserved 111_0010 reserved 111_0011 unused 111_0100 reserved 111_0101 reserved 111_0110 cr 8 r/w 0000 0000 2 control register 111_0111 as0 8 r/w 0100 0100 2 adc setup register 111_1000 reserved 111_1001 unused 111_101x unused 111_11xx unused table 8 : serial interface address map.
vv5404 & VV6404 cd5404-6404f-a 31/54 5.5.1 deviceh [000_0000 2 ] and devicel [000_ 0001 2 ] these registers provide read only information that identifies the sensor type that has been coded as a 12bit number and a 4bit mask set revision identifier. the device identification number for VV6404 is 404 i.e. 0001 1001 0100 2 . the initial mask revision identifier is 0 i.e. 0000 2 . 5.5.2 status0 [000_0010 2 ] 5.5.3 line_count_h [000_0011 2 ] & line_count_l [000_0100 2 ] bits function default comment 7:0 device type identifier 0001 1001 2 most significant 8 bits of the 12 bit code identifying the chip type. table 9 : deviceh [000_0000 2 ] bits function default comment 7:4 device type identifier 0100 2 least significant 4 bits of the 12 bit code identifying the chip type. 3:0 mask set revision identifier 0000 2 table 10 : devicel [000_0001 2 ] bit function default comment 0 exposure value update pending 0 exposure sent but not yet consumed by the exposure controller 1 gain value update pending 0 gain value sent but not yet consumed by the exposure controller 2 clock divisor update pending 0 clock divisor sent but not yet consumed by the exposure controller 3 black cal fail flag 0 if the black calibration has failed this flag will be raised. it will stay active until the last line of the next successful black calibration. 4 odd/even frame 1 the flag will toggle state on alternate frames 7:5 unused 000 table 11 : status0 [000_0010 2 ] register index bits function default comment 000_0011 2 7:0 current line count msb - displays current line count 000_0100 2 7:0 current line count lsb - table 12 : current line counter value.
vv5404 & VV6404 cd5404-6404f-a 32/54 5.5.4 setup0 [001_0000 2 ] 5.5.5 setup1 [001_0001 2 ] bit function default comment 0 low power mode: off /on 1 powers down the sensor array. the output databus goes to f h . on power-up the s ensor enters low power mode. 1 sleep mode: off /on 0 puts the sensor array into reset. the output databus goes to f h . 2 soft reset off /on 0 setting this bit resets the sensor to its power-up defaults. this bit is also reset. 3frame rate select: 25 fps or 30 fps 1 4 tri-state output data bus outputs enabled /tristate 0 on power up the data output pads d[3:0] are enabled by default. 7:5 unused table 13 : setup0 [001_0000 2 ] bit function default comment 1:0 black calibration mode selection 10 black calibration trigger selection. default setting bases decision on result of monitor test. see table below 2 reserved 3 enable immediate clock division update. off /on 0 allow manual change to clock division to be applied immediately 4 enable immediate gain update. off /on 0 allow manual change to gain to be applied immediately 5 enable additional black lines (lines 3-9) off /on 0 if enabled this bit will also enable the line immediately following the end of frame line 6 border rows and columns: masked or output 1 these extra pixels/rows are used in colour processing 7 pixel read-out order: unshuffled or shuffled 1 it is strongly recommended to use shuffled read-out. table 14 : setup1 [001_0001 2 ]
vv5404 & VV6404 cd5404-6404f-a 33/54 if the gain change trigger option has been selected then care should be taken when writing the new gain value if the immediate gain update option has been selected. it is strongly advised that the user should not write a new gain value between line 0 (the status line) and line 9 (the last black calibration line). if the gain values are written in a timed manner then no restriction applies. 5.5.6 setup2 [001_0010 2 ] 5.5.7 setup4 [001_0100 2 ] black cal mode[1] black cal mode[0] comment 0 0 no black calibration 01 always trigger black calibration 1 0 black calibration triggered by a failed monitor test 1 1 trigger black calibration only if the gain setting changes table 15 : black calibration mode bit function default comment 5:0 pixel counter reset value 31 note: for proper synchronisation this regis- ter should be written with the value 30. 7:6 unused table 16 : setup2[001_0010 2 ] bit function default comment 1:0 fst/qck pin modes 0 selection of fst, qck pin data 3:2 qck modes 0 when to output qck 5:4 reserved 0 reserved for lst modes in other sensors 7:6 fst modes 0 table 17 : setup4[001_0100 2 ] fst/qck pin mode[1:0] fst pin qck pin 00 fst slow qck 01 fst fast qck 1 0 fast qck slow qck 1 1 invert of fast qck fast qck table 18 : fst/qck pin selection
vv5404 & VV6404 cd5404-6404f-a 34/54 the option to enable the qclk during the data and control period of the line must not be selected if monochrome (shuffled or unshuffled) video has been selected. 5.5.8 setup5 [001_0101 2 ] it is important to note that although the output buffer driver strengths can be selected by writing to this register the programmed values cannot be read back by the serial inter face. qck mode[1:0] qck state 00off 0 1 free running 1 0 valid during data and cont rol per iod of line (see note) 1 1 valid only during data period of line table 19 : qck modes note: not currently verified. contact stmicroelectronics for further information if this mode is to be used. fst mode[1:0] fst state 00off 0 1 on - qualifies the status line 10reserved 11unallocated table 20 : fst modes bit function default comment 0 map serial interface register bits values on to the qck and fst pins off /on 0 1 serial interface bit for qck pin 0 2 serial interface bit for fst pin 0 3 output driver strength select 1 default setting selects 4ma driver 4 output driver strength select 0 default setting selects 4ma drivers 7:5 unused 0 table 21 : setup4[001_0101 2 ] mapping enable fst pin qck pin 0fstqck 1 su5[2] su5[1] table 22 : fst/qck pin selection
vv5404 & VV6404 cd5404-6404f-a 35/54 5.5.9 exposure control registers [010_0000 2 ] - [010_1001 2 ] there is a set of programmable registers which controls the sensitivity of the sensor. the registers are as follows: 1. fine exposure. 2. coarse exposure time. 3. gain. 4. clock division. the gain parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core. note: the external exposure (coarse, fine, clock division or gain) values do not take effect immediately. data from the serial interface is read by the exposure algorithm at the start of a video frame. if the user reads an exposure value via the serial interface then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor. between writing the exposure data and the point at which the data is consumed by the exposure logic, bit 0 of the status register is set. the gain value is updated a frame later than the coarse, fine and clock division parameters, since the gain is applied directly at the video output stage and does not require the long set up time of the coarse and fine exposure and the clock division. to eliminate the possibility of the s ensor array seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the exposure page of the serial inter face register map. thus if the 5 by tes of exposure and gain data is sent as an auto-increment sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. the range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum allowed. oeb_composite su5[4] su5[3] comments 0 0 0 drive strength = 2ma 0 0 1 default drive strength = 4ma 0 1 0 drive strength = 6ma 0 1 1 unallocated 1 x x outputs are not being driven therefore driver strength is irrelevant table 23 : output driver strength selection
vv5404 & VV6404 cd5404-6404f-a 36/54 notes: 1. the enable signal enabling the external adc functionality is the logical or of cr0[0] bit and the invert of the adcvdd pin. 2. the low-power select signal for the analogue circuitry is the logical or of pd0[0] and setup0[0]. register index bits function default comment 010_0000 2 7:0 fine msb exposure value 0 maximum mode dependent: 360 (30fps) / 438 (25 fps) 010_0001 2 7:0 fine lsb exposure value 010_0010 2 7:0 coarse msb exposure value 302 maximum: 302 010_0011 2 7:0 coarse lsb exposure value 010_0100 2 2:0 gain value 0 000: gain = 1 001: gain = 2 011: gain = 4 111: gain = 8 010_0101 2 1:0 clock divisor value 0 00: pixel clock = clki clock/2 01: pixel clock = clki clock/4 10: pixel clock = clki clock/8 11: pixel clock = clki clock/16 table 24 : exposure, clock rate and gain registers bit function default comment 0 standby off /on 0 powers down all analogue circuitry 1 power down - adc off /on 0 2 power down - adc top reference off /on 0 5:3 reserved 7:6 unused table 25 : control register cr [111_0110 2 ]
vv5404 & VV6404 cd5404-6404f-a 37/54 5.5.10 adc setup register as0 [111_0111 2 ] bit function default comment 1:0 adc clock fine delay setting 0 ns / 4 ns / 8 ns / 16 ns 00 00: clock delay = 0 ns (default) 01: clock delay = 4 ns 10: clock delay = 8 ns 11: clock delay = 16 ns 3:2 adc clock phase delay setting 0 / 90 / 180 / 270 01 00: phase delay = 0 01: phase delay = 90 (default) 10: phase delay = 180 11: phase delay = 270 5:4 pck clock fine delay setting 0 ns / 4 ns / 8 ns / 16 ns 00 00: clock delay = 0 ns (default) 01: clock delay = 4 ns 10: clock delay = 8 ns 11: clock delay = 16 ns 7:6 reserved 1 table 26 : adc setup register as0 [111_0111 2 ]
vv5404 & VV6404 cd5404-6404f-a 38/54 5.6 types of messages this section gives guidelines on the basic operations to read data from and write data to the serial interface. the serial interface supports variable length messages. a message may contain no data bytes, one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. ? write no data byte, only sets the index for a subsequent read message. ? single location multiple data write or read for monitoring (real time control) ? multiple location, multiple data read or write for fast information transfers. examples of these operati ons are given below. a full description of the internal registers is given in the previous section. for all examples the slave address used is 32 10 for writing and 33 10 for reading. the write address includes the read/write bit (the lsb) set to zero while this bit is set in the read address. 5.6.1 single location, single data write. when a random value is written to the sensor, the message will look like this: in this example, the fineh exposure register (index = 32 10 ) is set to 85 10 . the r/w bit is set to zero for writ ing and the inc bit (msbit of the index byte) is set to zero to disable automatic increment of the index after writing the value. the address index is preserved and may be used by a subsequent read. the write message is terminated with a stop condition from the master. 5.6.2 single location, single data read. a read message always contains the index used to get the first byte. this example assumes that a write message has already taken place and the residual index value is 32 10 . a value of 85 10 is read from the fineh exposure register. note that the read message is terminated with a negative acknowledge (a ) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. 5.6.3 no data write followed by same location read. when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. in this example, the gain value (index = 36 10 ) is read as 15 10 : figure 19 : single location, single write. s 32 10 a 0 32 10 a 85 10 a p start device ack address index data stop figure 20 : single location, single read. s 33 10 a 0 32 10 a 85 10 a p start device ack address index data stop
vv5404 & VV6404 cd5404-6404f-a 39/54 as mentioned in the previous example, the read message is terminated with a negative acknowledge (a ) from the master. 5.6.4 same location multiple data write. it may be desirable to write a succession of data to a common location. this is useful when the status of a bit,(e.g. requesting a new black calibration), must be toggled. the message sequence indexes setup1 register. if bit 1 is toggled low, high low this will initiate a fresh black calibration. this is achieved by writing three consecutive data bytes to the sensor. there is no requirement to re-send the register index before each data byte. 5.6.5 same location multiple data read when an exposure related value ( fineh, finel, coarseh, coarse l , gain or clk_div ) is written, it takes effect on the output at the beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure parameters). to signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written and is reset at the start of the next frame. this flag appears in status0 register and may be monitored by the bus master. to speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master acknowledges each byte read. in the next example, a fineh exposure value of 0 is written, the status register is addressed (no data byte) and then constantly read until the master terminates the read message. figure 21 : no data write followed by same location read. s a sr a a a p 32 10 36 10 33 10 36 10 15 10 a 0 0 no data write read index and data sa 0 10 a a a 32 10 17 10 2 10 0 10 a 0 write setup1 turn off abc toggle force black cal.. p figure 22 : same location multiple data write. sa 0a a a 32 10 33 10 32 10 0 10 a 0 sr a a a a 33 10 0 10 111a 0 sr write finel with zero address the status0 reg. a 10a read continuously... ...until flag reset p figure 23 : same location multiple data read.
vv5404 & VV6404 cd5404-6404f-a 40/54 5.6.6 multiple location write if the automatic increment bit is set, (msb of the index byte), then it is possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. an auto-increment write to the black calibration dac registers with their default values is shown in the following example. . 5.6.7 multiple location read in the same manner, multiple locations can be read with a single read message. in this example the index is written first, to ensure the exposure related registers are addressed and then all six are read note that a stop condition is not required after the negative acknowledge from the master. s a 128 16 a aa 32 10 113 10 128 16 1 incremental write p figure 24 : multiple location write. incremental read sa a 32 10 32 10 1 sr 33 10 aa 32 10 1 fineh a a p finel coarseh coarsel gain clk_div a a a a no data write incremental read figure 25 : multiple location read.
vv5404 & VV6404 cd5404-6404f-a 41/54 5.7 serial interface timing note 1: with 200pf capacitive load. it is recomm ended that pull-up resistors of 2.2k - 4 .7k are fi tted to both sda and scl lines. parameter symbol min. max. unit scl clock frequency fscl 0 100 khz bus free time between a stop and a start tbuf 2 - us hold time for a repeated start thd;sta 80 - us low period of scl tlow 320 - us high period of scl thigh 160 - us set-up time for a repeated start tsu;sta 80 - us data hold time thd;dat 0 - us data set-up time tsu;dat 0 - ns rise time of scl, sda tr - 300 (note1) ns fall time of scl, sda tf - 300 (note1) ns set-up time for a stop tsu;sto 80 - us capacitive load of each bus line (scl, sda) cb - 200 pf table 27 : serial interface timing characteristics sda scl thd;sta tr thigh tf tsu;dat thd;dat tsu;sta tsu;sto ... ... thd;sta tlow tbuf stop start stop start all values referred to the minimum input level (high) = 3.5v, and maximum input level (low) = 1.5v figure 26 : serial interface timing characteristics
vv5404 & VV6404 cd5404-6404f-a 42/54 6. clock signal vv5404 and vv 6404 generate a system clock when a quartz crystal or ceramic resonator circuit is c onnected to the clki and clko pins. the device can also be driven directly from an external clock source driving clk. if clki is generated for the video sensor by the receiving device it must be active during serial interface communications for at least 16 clock cycles before the serial communications start bit and for at least 16 cycles after the serial communications stop bit. the synchronisation input, sin, synchronises the clock divider logic in addition to the main clock generation and the video timing control block. . for greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency. the clock divisor serial register selects the input clock frequency divisor. the clock signal must be a square wave with a 50% (+/- 10%) mark:space ratio. table 28 specifies the maximum and minimum pixel clock frequencies for the module. table 29 and table 29 specify the relati onship betw een the input clock, clki, and the pixel clock frequency for the different settings of the sensors internal clock divider. this translates into a maximum input clock frequency of 7.15909 mhz if a clock divisor of 2 is used (the default - table 29). thus if a 14.31818 mhz crystal is used, only the 4, 8 and 16 clock divisors should be used (table 29). mhz minimum pixel rate 0.44744 maximum pixel rate 3.57954 table 28 : maximum and minimum pixel rates x1 c2 c1 r1 32 31 vv5/6404 cmos clock source r2 c1 = c2 = 47 pf r1 = 1 m w r2 = 510 w x1 = 14.31818 mhz clk clock division clki clko driver 32 31 vv5/6404 clk clock division clki clko figure 27 : camera clock sources
vv5404 & VV6404 cd5404-6404f-a 43/54 6.8 synchronising 2 or more cameras a rising edge on the sin pin re-synchronises the sensors internal video timing logic and clock generators to 5 pixels before the end of the start of frame control s equence in l ine 0 (assuming the setup2 register has been programmed correctly with the value 30). by supplying an external timing signal to sin, with a period equal to 2 frames (see figure 28), 2 or more cameras can be synchronised together. for proper synchronisation, the pixel counter register setup2 must be written with 30, which will cause sin to reset the video timing to 5 pixel periods before the end of the start of frame control sequence. sin is sampled internally by the system clock, cki. if all cameras are supplied with the same clock signal then the reset genera ted by sin will synchronise all the cameras to the same point in time. however, if the cameras being synchronised are running at the same frequency but each camera has its own crystal, then there could be upto one system clock period of skew between the cameras. this skew will vary over time due to the slight mis-matches between frequencies of the different crystals. . clki (mhz) clock div reg divisor pixel frequency (mhz) frame rate (fps) comments bit 1 bit 0 30 fps 25 fps 7.15909 0 0 2 3.57954 30.0 25.0 default 7.15909 0 1 4 1.78977 15.0 12.5 7.15909 1 0 8 0.89489 7.50 6.25 7.15909 1 1 16 0.44744 3.75 3.125 table 29 : clock divisors for an externally generated clock signal. clki (mhz) clock div reg divisor pixel frequency (mhz) frame rate (fps) comments bit 1 bit 0 30 fps 25 fps 14.31818 0 0 2 7.15909 not valid 14.31818 0 1 4 3.57954 30.0 25.0 14.31818 1 0 8 1.78977 15.0 12.5 14.31818 1 1 16 0.89489 7.50 6.25 table 30 : clock divisors for a 14.31818 mhz crystal
vv5404 & VV6404 cd5404-6404f-a 44/54 figure 28 : synchronisation waveforms start of frame black lines blanking lines visible lines end of frame blanking lines blanking lines 1st frame (ii) on end of frame fst: (ii) off start of frame black lines blanking lines visible lines end of frame blanking lines 2nd frame start of frame sav eav eav status information synchronisation input (at sin pin) from the master (e.g. vi deo pr ocessor). line period (393 pixel periods - 30 fps, 471 pixel periods - 25 fps) 356 pixels 37 (115) pixels 4 pixels 33 (111) pixels sav eav eav output of slave 2 - pixel counter reset value = 30. 1 pixel period start of frame line format: status information frame format: (iii) sync input at sin (if external synchronisation required))
vv5404 & VV6404 cd5404-6404f-a 45/54 7. detailed specifications 7.1 general * contact stmicroelectronics for information regarding increased temperature range 7.2 dc characteristics image format 356 x 292 pixels (cif) pixel size 12.0 x 11.0 m m array format cif exposure control 25000:1 (performed by co-processor) sensor signal / noise ratio 46db minimum illumination 0.1 lux supply voltage 5.0v dc +/-5% package type 48lcc operating temp. range 0 o c - 40 o c* serial interface frequency range 0-100khz supply voltage 5.0 v dc +/- 5% supply current < 75 ma package type 48bga table 31 : vv5407/6407 specifications parameter min. max. notes v il -0.5v 0.3 x v dd guaranteed input low voltage v ih 0.7 x v dd v dd + 0.5v guaranteed input high voltage v ol 0.4v at max i ol for pad type v oh 2.4v v dd - 0.5v ioh = 100 m a at max i oh for pad type t j junction temp 0 deg c 100 deg c internal pullup resistor 35k w 150k w internal pulldown resistor 35k w 150k w table 32 : vv5407/6407 dc characteristics
vv5404 & VV6404 cd5404-6404f-a 46/54 8. physical 8.1 pinout diagram (dnc) - do not connect these pins (*) - paddle connections clki clko d[0] d[1] vdd3 vss3 dvss/dsub vbltw vbg vcds avcc agnd (*) vvss adcvss (*) adcvdd vdd1 vss1 sin 7 8 6 5 4 3 2 1 48 47 46 45 44 42 41 38 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 d[2] d[3] fst sda scl 48 pin lcc vcm / vref2v5 avss vbloom adcbot 40 39 18 30 31 43 (dnc) avdd qck vvdd oeb/sci resetb topref/adctop holdpix vrt vss2 vdd2 (dnc) dvdd (dnc) (dnc) (dnc) (dnc) (dnc) (dnc) (dnc) (dnc) vv5/6404 figure 29 : pinout
vv5404 & VV6404 cd5404-6404f-a 47/54 8.2 signal names pin name type description power supplies 1 avcc pwr core anal ogue power and reference supplies. 48 agnd gnd core analogue ground and reference supplies. 43 dvdd pwr core digital power. 44 dvss/dsub gnd core digital ground. 6 avdd pwr output stage power. 5 avss gnd output stage ground. 7 vvdd pwr analogue output buffer power. 9 vvss gnd analogue output buffer ground. 14 adcvdd pwr adc power. 10 adcvss gnd adc ground. 19 vdd1 pwr digital padring & logic power. 30 vdd2 pwr digital padring & logic power. 36 vdd3 pwr digital padring & logic power. 20 vss1 gnd digital padring & logic ground. 29 vss2 gnd digital padring & logic ground. 37 vss3 gnd digital padring & logic ground. analogue signals 45 vbloom oa anti-blooming pixel reset voltage 46 vbltw oa bitline test white level reference 47 vbg oa internally generated bandgap reference voltage 1.22v 2vcm/ vref2v5 oa common-mode input for osa and internally generated 2.5 v reference voltage. 3 vrt ia pixel reset voltage 4 vcdsh ia 8 avo oa analogue test output 11 adcbot ia bottom voltage reference for adc 12 holdpix ia not for customer use 13 topref oa internally generally top voltage reference for adc
vv5404 & VV6404 cd5404-6404f-a 48/54 pin name type description digital control signals 18 sce id test pin 15 sin id frame timing reset (soft reset). 16 resetb id - system reset. active low. serial interface 42 scl id - serial bus clock (input only). 41 sda bi - serial bus data (bidirectional, open drain). digital video interface 39 38 35 34 d[3] d[2] d[1] d[0]] odt tristateable 4-wire output data bus. d[3] is the most significant bit. 33 qck odt tristateable data qualification clock. 40 fst odt tristateable frame start signal. 17 oeb id digital output (tristate) enable. system clocks 31 clki id oscillator input. 32 clko od oscillator output. key a analogue input d digital input oa analogue output id - digital input with inter nal pull-up bi bidirectional id digital input with inter nal pull-down bi - bidirectional with internal pull-up od digital output bi bidirectional with internal pull-down odt tristateable digital output
vv5404 & VV6404 cd5404-6404f-a 49/54 8.3 48lcc mechanical dimensions
vv5404 & VV6404 cd5404-6404f-a 50/54 8.4 VV6404 sensor support circuit schematic diagram 8.5 sensor support circuit component list c1 c4 ic1 16 36 32 31 1 45 3 6 47 46 15 19 (48 pin lcc) 43 7 34 38 35 39 42 41 12 13 11 20 29 37 44 5 2 c2 48 scl clki sda d[3] d[1] d[2] d[0] d[3] d[2] d[1] d[0] adcvdd adcvss scl sda resetb vcm / vref2v5 vbloom vrt vbltw vvss vvdd vcdsh vbg adcbot holdpix adctop/topref qck fst oeb sin vss1 vss2 vss3 vdd3 vdd2 vdd1 dvdd dvss avss agnd 4 33 40 clki clko c15 c5 17 10 9 c13 c14 c16 avcc avdd 30 14 c4 c3 c8 c6 vv5/6404 r3 dvdd/avdd r4 r5 c11 c12 r2 r1 tp1 c10 avdd dvdd c7 c9 +5v dc 0v dgnd agnd
vv5404 & VV6404 cd5404-6404f-a 51/54 notes: 1. use surface mount components throughout. 2. all ceramic capacitors are type cog. 3. keep nodes supply and ground pins low impedance and independent. 4. keep circuit components close to chip pins (especially de-coupling capacitors). 5. emc precautions will be required on d[3:0] if driving a longer cable. component part no. / provisional value rating / notes ic1 VV6404a vvl camera chip (48 pin lcc) c1 10.0 m f6v tant. c2-c3, c4-c6, c7-c8 0.1 m f c9-c10 10.0 m f 6v tant. c11-c12 220pf(*) for 3m cable length c13-c14 0.1 m f c15 4.7 m f 6v tant c16 10.0 m f 6v tant tdb r1-r2 voltage divider such that tp1 = 3.2v r3 33 w r4-r5 2k2 w(*) for 3m cable length table 33 : pcb component list
vv5404 & VV6404 cd5404-6404f-a 52/54 9. ordering information part number description defect specification vv5404c001 cif resolution monochrome digital cmos image sensor, 48 pin lcc package zero defects VV6404c001 cif resolution colour digital cmos image sensor, 48 pin lcc package zero defects VV6404c001-b2 cif resolution colour digital cmos image sensor, 48 pin lcc package up to 36 defects for use when pixel defect correction is implemented stv5404e-001 evaluation kit for vv5404 sensor n/a stv6404e-001 evaluation kit for VV6404 sensor n/a
vv5404 & VV6404 cd5404-6404f-a 53/54
vv5404 & VV6404 cd5404-6404f-a 54/54 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved . vlsi vision l imited a company of the st microelectronics group ? www.vvl.co.uk www.st.com asiapacific_sales@vvl.co.uk central_europe_sales@vvl.co.uk france_sales@vvl.co.uk japan_sales@vvl.co.uk nordic_sales@vvl.co.uk southern_europe_sales@vvl.co.uk uk_eire_sales@vvl.co.uk usa_sales@vvl.co.uk

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